1. Field of the Invention
The present invention relates to fabrication methods of semiconductor packages, and more particularly, to a fabrication method of a semiconductor package for improving the product reliability.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed towards multi-function and high electrical performance. Accordingly, fan out packaging technologies have been developed to meet the miniaturization requirement of semiconductor packages.
FIGS. 1A to 1D are schematic cross-sectional views showing a fabrication method of a fan out semiconductor package 1 according to the prior art.
Referring to FIG. 1A, a carrier 10 is provided and an adhesive layer 11 is formed on the carrier 10.
Then, a plurality of semiconductor elements 12 are disposed on the adhesive layer 11. Each of the semiconductor elements 12 has an active surface 12a with a plurality of electrode pads 120 and a non-active surface 12b opposite to the active surface 12a. The semiconductor elements 12 are attached to the adhesive layer 11 via the active surfaces 12a thereof.
Referring to FIG. 1B, an encapsulant 13 is laminated on the adhesive layer 11 for encapsulating the semiconductor elements 12.
Referring to FIG. 1C, a curing process is performed to cure the encapsulant 13, and then the adhesive layer 11 and the carrier 10 are removed to expose the active surfaces 12a of the semiconductor elements 12.
Referring to FIG. 1D, an RDL (Redistribution Layer) process is performed to form an RDL structure 14 on the encapsulant 13 and the active surfaces 12a of the semiconductor elements 12. The RDL structure 14 is electrically connected to the electrode pads 120 of the semiconductor elements 12.
Then, an insulating layer 15 is formed on the RDL structure 14, and portions of the RDL structure 14 are exposed from the insulating layer 15 so as for a plurality of conductive elements 16 such as solder bumps to be mounted thereon.
However, large stresses may be generated during the curing process of the encapsulant 13 and dispersed by the carrier 10. As such, referring to FIG. 1D′, warpage easily occurs on edges of the encapsulant 13 after the carrier 10 is removed. Therefore, it becomes difficult for the RDL structure 14 to be aligned with the electrode pads 120 of the semiconductor elements 12. The greater the size of the carrier 10 is, the more severe the position tolerance between the semiconductor elements 12 becomes, thereby adversely affecting the electrical connection between the RDL structure 14 and the semiconductor elements 12. As such, the product reliability and yield are reduced.
Therefore, there is a need to provide a fabrication method of a semiconductor package so as to overcome the above-described drawbacks.